A conventional semiconductor memory apparatus of a complementary bit line type comprises a predetermined number of memory cells to provide a desired memory capacity, a predetermined number of complementary bit line pairs, among which each two complementary bit line pairs are connected to a corresponding memory cell to provide dual ports, a predetermined number of word lines, two of which word lines are connected to a corresponding memory cell to allow asynchronous access for the dual ports, and a predetermined number of sense amplifier (defined "amp" hereinafter) circuits each connected to one of the complementary bit line pairs.
In operation, it is assumed that each of the complementary bit line pairs is under "high" at first in accordance with the initialization of the memory apparatus. When a word selection signal becomes "high" on a word line for a first selected port, a signal level difference begins to be produced between bit lines of a complementary bit line pair for the first selected port dependent on a content of a memory cell. Subsequently, when a word signal becomes "high" on a word line for a second selected port, a signal level difference begins to be produced between bit lines of a complementary bit line pair for the second selected port dependent on the content of the memory cell in the same manner as in the first selected port. At this moment, a sense amp circuit connected to the bit lines for the first selected port is enabled to amplify and stabilize the signal level difference. Thus, information is read from a port corresponding to a selected memory cell. The structure and operation of the conventional semiconductor memory apparatus of the complementary bit line type will be explained in more detail later.
According to the conventional semiconductor memory apparatus, however, there are disadvantages that an erasure or a destruction of information occurs in a memory cell, and that erroneous information is read from a memory cell, because a signal level is pulled, for instance, from "high" to "low" on a bit line of the second selected port under the influence of a signal level on a bit line of the first selected port, where the bit lines of the first and second selected ports are heavily coupled by a line-to-line capacitance produced therebetween. This results in an inversion of a readout information at the second selected port.
These disadvantages will be overcome, if the line-to-line capacitance is lowered to a predetermined level between adjacent bit lines of the dual ports, or if accesses are synchronized between the dual ports. For this purpose, the length of bit lines must be shortened to reduce the line-to-line capacitance, making it difficult to increase the memory capacity. Further, access control of the dual ports will be complicated.